FIG. 14 is a schematic cross-sectional representation of a trench n-type MOSFET device 100 of the prior art. It has a gate region that includes a trench 108 with gate dielectric 109 located on its sidewalls and floor. Trench 108 is filled with polysilicon 110 serving as a gate electrode. Source connection is achieved through the top metal 112 connected to both the source and body regions 106 and 104, respectively. The back side of the N+ substrate 101 is used as a drain.
N+ source regions 106 are formed in P-well regions 103, which extend to the corners of the trenches and can cause the formation of large electric fields. The P+ body implants 104, which are made are made to lower the breakdown voltage of P-wells 103, are large and thus reduce the active area of device 100. Although only one MOSFET is shown in FIG. 14, a typical device consists of an array of them arranged in various cellular or stripe configurations currently used by the industry.